Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
Background Art
Conventionally, as a test to detect a failure in a semiconductor device, evaluations of electrical characteristics of a semiconductor device are made by bringing a probe into contact with the semiconductor device in a wafer state after the completion of a wafer process and applying a bias through the probe (see, for example, Japanese Patent No. 3279294 and Japanese Patent Laid-Open No. 02-181457). In some cases, a contact pad for testing is prepared to avoid contact between the probe and a structural member such as a bump on the wafer surface and a test is made by electrically connecting the contact pad to the bump.
In the conventional failure detection method, at least the completion of all wiring layers must be awaited before testing a manufactured semiconductor device. However, semiconductor devices recently developed have a plurality of wiring layers because of the progress of schemes to improve the degree of integration, and losses of time and manufacturing cost are large in a case where a failure is found after all the wiring layers are formed. Further, in some cases of testing a completed semiconductor device, there is a possibility of a failure to make a test about an important parameter depending on the circuit configuration or occurrence of a restriction on a testing condition.